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This paper analyzes the performance of different interconnect technologies for on-chip clock distribution, including conventional, three-dimensional, optical, and radio frequency interconnects. Skew, power, and area usage were estimated for each of these technologies based on the 2001 International Technology Roadmap for Semiconductors. Our results indicate that most of the skew and power are associated with local clock distribution. Consequently, since the alternative clock distribution approaches that have been proposed focus on global clock distribution, we have not found significant advantages over conventional clock distribution in terms of skew and power. Furthermore, it was found that low skews could be attained with conventional clock distribution schemes if the clock signals are not scaled down.