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Checkpoint processing and recovery: an efficient, scalable alternative to reorder buffers

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3 Author(s)
Akkary, H. ; Portland State Univ., OR, USA ; Rajwar, R. ; Srinivasan, S.T.

Processors require a combination of large instruction windows and high clock frequency to achieve high performance. Traditional processors use reorder buffers, but these structures do not scale efficiently as window size increases. A new technique, checkpoint processing and recovery, offers an efficient means of increasing the instruction window size without requiring large, cycle-critical structures, and provides a promising microarchitecture for future high-performance processors.

Published in:

Micro, IEEE  (Volume:23 ,  Issue: 6 )

Date of Publication:

Nov.-Dec. 2003

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