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The coupling noise immune electrostatic discharge (ESD) protection network is becoming a critical design requirement for preserving the performance of high-speed analog circuits. In this paper, we present a noise-aware design of ESD power protection with diode structures in highly integrated high-speed CMOS ICs. We thoroughly characterize the noise coupled from the ESD power protection network and experimentally verify its generation and impact on the performance of analog circuitry being protected. A noise-aware design technique is proposed to achieve superior noise isolation while improving ESD reliability. The estimation of peak overvoltage on power/ground busses in digital circuits adaptively finds the optimum feature of protection circuits subject to noise constraints. The design is validated with measurements from a test chip fabricated in a 0.18-μm CMOS technology.