By Topic

A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)
Hamamoto, T. ; Memory Design Dept., Renesas Technol. Corp., Hyogo, Japan ; Furutani, K. ; Kubo, T. ; Kawasaki, S.
more authors

This paper describes an all-digital delay-locked loop (DLL) architecture for over 667 Mb/s operating double-data-rate (DDR) type SDRAMs, which suppresses skews and jitters. Two novel replica adjusting techniques are introduced, in which timing skews caused by the clock input and data output circuits are reduced by a hierarchical phase comparing architecture and a replica check method with slow tester. Further, an improved phase interpolating method suppresses jitters caused by a boundary of the fine and coarse delays. A 512-Mb test device is fabricated using a 0.13-μm DRAM process technology, in which skew and jitter suppressed 667-Mb/s (333-MHz) DDR operation has been verified.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:39 ,  Issue: 1 )