Cart (Loading....) | Create Account
Close category search window
 

A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS/s output for DDFS system in 0.35-μ hboxm CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Seng-Pan U ; Fac. of Sci. & Technol., Univ. of Macau, Macao, China ; Martins, R.P. ; Franca, J.E.

A switched-capacitor (SC) bandpass interpolating filter is proposed with the capability of achieving, simultaneously, channel selection and frequency up-translation, together with sampling rate increase, in a multirate configuration at high frequency. This filter has been designed for efficient use in a direct-digital frequency synthesis (DDFS) system with considerable rewards in terms of speed reduction of the digital core plus the digital-to-analog converter (DAC), as well as in the relaxation of the continuous-time (CT) smoothing filter order. It exhibits a 15-tap finite impulse response (FIR), with a bandpass frequency response centered at 57 MHz and a stop-band rejection higher than 45 dB. At the same time, it translates 22-24 MHz input signals at 80 MS/s, to the frequency range of 56-58 MHz in the output at 320 MS/s, allowing also a perfect operation at 400 MS/s, in 0.35-μm CMOS technology. To implement a specific multi-notch FIR function, the filter architecture will comprise an effective low-speed polyphase-based interpolation structure with autozeroing capability, high-speed SC circuitry with fast opamps, and also ultra-low timing-skew multiple phase generation in order to achieve high-performance operation at high frequency. The prototype ICs present a signal-to-noise-and-distortion ratio (SNDR) of 61 dB, with a dynamic range of 69 dB, for 1% THD, and 61 dB, for 1% IM3. It consumes 2 mm2 of active silicon area, 120 mW (analog) and 16 mW (digital) power, with a single 2.5-V supply, which corresponds to 8.6 mW of analog power per zero.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:39 ,  Issue: 1 )

Date of Publication:

Jan. 2004

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.