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This paper presents the design and experimental results of a continuous-time ΣΔ modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity. The nonzero excess loop delay problem in conventional continuous-time ΣΔ modulators is solved by our proposed architecture. A prototype third-order continuous-time ΣΔ modulator with 5-bit internal quantization was realized in a 0.5-μm double-poly triple-metal CMOS technology, with a chip area of 2.4 × 2.4 mm2. Experimental results show that the modulator achieves 88-dB dynamic range, 84-dB SNR, and 83-dB SNDR over a 1.1-MHz signal bandwidth with an oversampling ratio of 16, while dissipating 62 mW from a 3.3-V supply.
Date of Publication: Jan. 2004