Notification:
We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

Reconfigurable hardware implementation of an improved parallel architecture for MPEG-4 motion estimation in mobile applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Gao, R. ; Sch. of Sci. & Technol., Teeside Univ., Middlesbrough, UK ; Xu, D. ; Bentley, J.P.

A reconfigurable hardware implementation of a high-parallel architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low power dissipation and low cost, thus primarily aiming at video-based mobile applications. The architecture employs a dual-register/buffer technique to reduce preload and alignment cycles and a high-parallel pipeline to reduce power consumption of redundant memory access. As an example, a content-based full-search block-matching algorithm has been mapped onto this architecture using a 16-PE array. This has the ability to calculate the motion vectors of 20 fps QCIF video sequences in real time at 8.2 MHz clock rate with 36.7 mW power dissipation using Xilinx Spartan II FPGA.

Published in:

Consumer Electronics, IEEE Transactions on  (Volume:49 ,  Issue: 4 )