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Instruction-based delay fault self-testing of processor cores

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4 Author(s)
Singh, V. ; Nara Inst. of Sci. & Technol., Japan ; Inoue, I. ; Saluja, K.K. ; Fujiwara, H.

This paper proposes an efficient methodology of delay fault testing of processor cores using its instruction set. These test vectors can be applied in the functional mode of operation, hence, self-testing of processor core becomes possible. Path delay fault model is used. The proposed approach uses a graph theoretic model (represented as an Instruction Execution Graph) of the datapath and a finite state machine model of the controller for the elimination of functionally untestable paths at the early stage without looking into the circuit details and extraction of constraints for the paths that can potentially be tested. Parwan processor is used to demonstrate the effectiveness of our method.

Published in:

VLSI Design, 2004. Proceedings. 17th International Conference on

Date of Conference:

2004