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The digital design paradigm is in transition. We discuss on-chip programmable regulators to reduce power consumption; SERDES blocks to reduce the inter-block interconnections and small signal swing high-speed differential inputs and outputs to maximize performance in interconnect delay-dominated technologies. We need to build re-configurability and re-use of logic as an essential feature of device functionality. We need to adopt self-calibration mechanisms to solve the timing closure problem and find ways to reduce the cost of test by design.