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A novel technique for steady state analysis for VLSI circuits in partially depleted SOI

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3 Author(s)
Joshi, R.V. ; T.J. Watson Res. Center, IBM, Yorktown Heights, NY, USA ; Kroell, K. ; Chuang, C.T.

This paper presents a computationally efficient technique for accurate analysis of floating-body partially depleted SOI (PD/SOI) CMOS circuits in steady state operating mode. The basic algorithm and techniques to improve the convergence and reduce simulation time are described. The methodology provides over 2 orders of magnitude improvement in simulation time compared with straightforward circuit simulation for large multiple-input circuit macros and SRAMs, thus allowing accurate analysis/assessment of the history effect in PD/SOI CMOS circuits and body voltage and Vt drifts in sensitive circuits.

Published in:

VLSI Design, 2004. Proceedings. 17th International Conference on

Date of Conference:

2004