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ILP models for energy and transient power minimization during behavioral synthesis

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3 Author(s)
Mohanty, S.P. ; Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA ; Ranganathan, N. ; Chappidi, S.K.

The reduction of peak power, peak power differential, average power and energy are equally important in the design of low-power battery driven portable applications. In this paper, we introduce a parameter called "cycle power function" (CPF-DFC) that captures the above power characteristics in the context of multiple supply voltage (MV) and dynamic frequency clocking (DFC) based designs. Further, we present ILP formulations for the minimization of CPF-DFC during datapath scheduling. We conducted experiments on selected high-level synthesis benchmarks for various resource constraints. Experimental results show that significant reduction in power, energy, and energy delay product, can be obtained using the proposed method.

Published in:

VLSI Design, 2004. Proceedings. 17th International Conference on

Date of Conference: