By Topic

ILP models for energy and transient power minimization during behavioral synthesis

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Mohanty, S.P. ; Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA ; Ranganathan, N. ; Chappidi, S.K.

The reduction of peak power, peak power differential, average power and energy are equally important in the design of low-power battery driven portable applications. In this paper, we introduce a parameter called "cycle power function" (CPF-DFC) that captures the above power characteristics in the context of multiple supply voltage (MV) and dynamic frequency clocking (DFC) based designs. Further, we present ILP formulations for the minimization of CPF-DFC during datapath scheduling. We conducted experiments on selected high-level synthesis benchmarks for various resource constraints. Experimental results show that significant reduction in power, energy, and energy delay product, can be obtained using the proposed method.

Published in:

VLSI Design, 2004. Proceedings. 17th International Conference on

Date of Conference: