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Net buffering in the presence of multiple timing views

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1 Author(s)
Murgai, R. ; Fujitsu Labs. of America, Inc., Sunnyvale, CA, USA

Several modern complex digital designs involve multiple clock domains. For instance, it is not uncommon to see telecommunication chips having three to thirty clock domains. Timing views are a way to represent multiple sets of timing information at a circuit node. In this paper, we address the optimization problem of net buffering in the presence of multiple timing views. To the best of our knowledge, this is the first time that this problem has been addressed in the literature. We propose a technique which considers simultaneously all the timing views at a node and is efficient, effective, and robust. Experimental results on large industrial designs show that our technique yields better quality results and runs up to 5.75 times faster as compared to an iterative technique which works on one timing view at a time.

Published in:

VLSI Design, 2004. Proceedings. 17th International Conference on

Date of Conference: