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Sizing consideration for leakage control transistor

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4 Author(s)
Farbiz, F. ; Dept. of Electr. & Comput. Eng., Tehran Univ., Iran ; Farazian, M. ; Emadi, M. ; Sadeghi, K.

In this paper, we report the use of the Genetic Algorithm (GA) to determine the optimum size of the leakage control transistor for low power applications. In the optimization, the energy-delay product is minimized. The transistor is modeled by a neural network to increase the speed and the accuracy of the calculations.

Published in:

VLSI Design, 2004. Proceedings. 17th International Conference on

Date of Conference:

2004