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A novel technique towards eliminating the global clock in VLSI circuits

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4 Author(s)

As the feature size offered by VLSI technology shrinks, circuit performance as well as circuit complexity increases. This puts considerable pressure on the synchronous design methodology, mainly due to the difficulty of routing a low skew high frequency clock signal across a large die. On the other hand, the synchronous design methodology offers the benefits of a mature design flow and a comprehensive set of design tools. In this paper, we present an approach towards the elimination of the global clock signal in a synchronous design. We present a novel partitioning strategy and the design of a distributed asynchronous controller for this purpose. The transformed circuit can have performance comparable or possibly superior to the original synchronous circuit (provided clock could be distributed in the first place). The technique is demonstrated by a pilot design in a .18 micron TSMC process, and is a good candidate for a clock-less design methodology built around the principle of desynchronization.

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VLSI Design, 2004. Proceedings. 17th International Conference on

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