By Topic

Package-silicon co-design-experiment with an SOC design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
P. R. Suresh ; Texas Instrum. India Ltd., Bangalore, India ; P. K. Sundararajan ; A. Goel ; H. Udayakumar
more authors

In this paper, we describe a package-silicon co-design approach attempted for an RF integrated SOC design. Extensive simulations were carried out to determine the sensitivity of different package layout parameters on signal integrity and noise related issues. These experiments helped in influencing the package layout design and the custom I/O cell design. The I/O and core bump locations, and the package via locations were determined based on the reliability and noise considerations. Both the floorplanning and package layout were fine tuned to optimize the area and signal integrity issues. This was followed by extensive package simulations to determine the SSN and crosstalk numbers.

Published in:

VLSI Design, 2004. Proceedings. 17th International Conference on

Date of Conference: