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In this paper, we describe a package-silicon co-design approach attempted for an RF integrated SOC design. Extensive simulations were carried out to determine the sensitivity of different package layout parameters on signal integrity and noise related issues. These experiments helped in influencing the package layout design and the custom I/O cell design. The I/O and core bump locations, and the package via locations were determined based on the reliability and noise considerations. Both the floorplanning and package layout were fine tuned to optimize the area and signal integrity issues. This was followed by extensive package simulations to determine the SSN and crosstalk numbers.