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Design, analysis, and implementation of analog complex filter for low-IF Wireless LAN application

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4 Author(s)
T. H. Teo ; Integrated Circuit & Syst. Lab., Inst. of Microelectron., Singapore, Singapore ; E. -S. Khoo ; D. Uday ; C. -B. Tear

The design and implementation of an analog complex filter for low-IF WLAN 802.11a receiver is described. An IF of 20 MHz is chosen as a trade off between image-rejection and power consumption. The specified bandwidth is 20 MHz. Baseband processing requires low group-delay variation in the received signal to meet bit error rate (BER) specification. This requires a design of high frequency, wide bandwidth and high attenuation filter. To resolve these issues, fifth-order complex transitional Bessel-Chebyshev filter is implemented to compromise between high attenuation and low group-delay variation. Measured results show the designed filter provides 30 dB to 40 dB image rejection and 18 dB adjacent channel rejection, while keeping a low group-delay variation of below 6.0 ns within the pass-band. High frequency and wide bandwidth filter also requires stringent design specification of the circuitries. Differential inverter transconductor is optimized for this continuous-time filter design. The complete filter including on-chip tuning circuit and bandgap consumes only 7.5 mA with 1.8 V single supply voltage. The circuit is fabricated using 0.18 μm, 6-metal-single-poly CMOS process.

Published in:

VLSI Design, 2004. Proceedings. 17th International Conference on

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