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Bridge over troubled wrappers:automated interface synthesis

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3 Author(s)

System-on-Chip (SoC) design methodologies rely heavily on reuse of intellectual property (IP) blocks. IP reuse is a labour intensive and time consuming process as IP blocks often have different communication interfaces. We present an algorithm which automates the generation of provably correct HDL descriptions of interfaces between mismatched IP communication protocols. We significantly improve and extend existing work by providing a solution which addresses data mismatches, pipelining and differences in clock speeds. These ideas have been implemented and the tool has been used to synthesise wrappers and bridges for many SoC protocols.

Published in:

VLSI Design, 2004. Proceedings. 17th International Conference on

Date of Conference:

2004