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Error correction in pipelined ADCs using arbitrary radix calibration

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3 Author(s)
Savla, A. ; Dept. of Comput. & Electr. Eng., Ohio State Univ., Columbus, OH, USA ; Leonard, J. ; Ravindran, A.

This paper presents an ADC architecture which enhances accuracy of pipelined conversion using digital calibration. The popular 1.5 bit/stage pipeline architecture is adapted to an arbitrary radix structure. Calibration algorithms that estimate gain errors for two comparators in each pipeline stage are developed using this architecture. A low-noise queueing technique which enables calibration to be performed in background without interrupting the ADC input sample stream is presented. A 12-stage pipeline ADC model is used to demonstrate the effectiveness of calibration algorithms. With 10% error in the interstage gain, calibration improves the accuracy from 5 to 11 bits. Effects of implementation issues such as gain parameter settling, intradie gain variation, and finite word length computation are studied.

Published in:

VLSI Design, 2004. Proceedings. 17th International Conference on

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