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Property refinement techniques for enhancing coverage of formal property verification

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4 Author(s)
P. Basu ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India ; P. Dasgupta ; P. P. Chakrabarti ; C. R. Mohan

Coverage metrics for formal property verification (FPV) are gaining in significance as most chip design companies are adopting formal methods within a predominantly simulation based validation flow. Researchers have observed that typical correctness properties exhibit a low amount of coverage since they check for the absence of invalid runs, rather than the existence of valid runs. In this paper, we show that feedback from FPV can be effectively used to refine an existing specification to obtain better coverage. We propose an interactive methodology for specification refinement, and present formal methods for implementing this methodology.

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VLSI Design, 2004. Proceedings. 17th International Conference on

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