By Topic

Formal verification of modules under real time environment constraints

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
A. Banerjee ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India ; P. Dasgupta ; P. P. Chakrabarti

Recent approaches to modular verification rely on appropriate modeling of the environment under which the module is exercised. In order to apply model checking techniques on open systems, an appropriate notion of fairness of the environment is required. This paper proposes a formal approach for modular verification in the presence of untimed as well as real time constraints on the environment. In this paper, we address (possibly for the first time) the problem of formal verification of open systems under real-time fairness constraints on the environment. We show that determining the consistency of a set of real time environment constraints is NP hard, but inconsistencies in the specification can be avoided by some simple restrictions.

Published in:

VLSI Design, 2004. Proceedings. 17th International Conference on

Date of Conference: