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Formal verification of modules under real time environment constraints

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3 Author(s)
Banerjee, A. ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India ; Dasgupta, P. ; Chakrabarti, P.P.

Recent approaches to modular verification rely on appropriate modeling of the environment under which the module is exercised. In order to apply model checking techniques on open systems, an appropriate notion of fairness of the environment is required. This paper proposes a formal approach for modular verification in the presence of untimed as well as real time constraints on the environment. In this paper, we address (possibly for the first time) the problem of formal verification of open systems under real-time fairness constraints on the environment. We show that determining the consistency of a set of real time environment constraints is NP hard, but inconsistencies in the specification can be avoided by some simple restrictions.

Published in:

VLSI Design, 2004. Proceedings. 17th International Conference on

Date of Conference:

2004