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Formal verification of C language based VLSI designs

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1 Author(s)
Fujita, M. ; Dept. of Electron. Eng., Tokyo Univ., Japan

This paper discusses about formal verification techniques targeting C based VLSI design descriptions. Recently there are lots of attentions into the use of C programming language (or its extensions) for describing hardware as well as software with an intention to support hardware-software co-design processes with a single language. Here we first discuss about such design methodologies by which system level descriptions for hardware-software combined systems can be uniformly and smoothly refined into implementation in RTL for hardware and assembly languages for software. Starting from regular C programming language descriptions, the design methodologies repeat a number of small refinement steps and gradually adding more and more details into the target designs. We also discuss about formal verification of system level descriptions in those design methodologies from the viewpoint of formal verification. Since such descriptions have essentially concurrency and C must be extended to be able to represent such concurrency, an effective and efficient formal verification of synchronization of concurrent processes is one of the most important issues in system level designs. We present model checking and equivalence checking methods targeting the design methodology that can check correctness of design descriptions with preliminary experimental results. The proposed formal verification methods will support the design methodologies and are very efficient by utilizing the fact that the design methodologies consist of lots of small refinement steps.

Published in:

VLSI Design, 2004. Proceedings. 17th International Conference on

Date of Conference:

2004