By Topic

Design challenges in sub-100 nm high performance microprocessors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Narendra, S.G. ; Circuit Res.-Intel Labs., Intel Corp., Hillsboro, OR, USA ; Tschanz, J. ; Erraguntla, V. ; Borkar, N.

This article deals with design challenges for high performance microprocessors. Device challenges including gate leakage, junction tunneling, junction depth scaling, parasitic series resistance, and short channel effects. Microprocessor frequencies are increasing every generation from additional architectural and circuit complexity, which demands higher level of integration and die size increase. To address these scaling challenges, devices, circuits and design methodologies need to evolve. Scaling gate oxide thickness is important for controlling short channel effects.

Published in:

VLSI Design, 2004. Proceedings. 17th International Conference on

Date of Conference: