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Design challenges in sub-100 nm high performance microprocessors

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4 Author(s)
Narendra, S.G. ; Circuit Res.-Intel Labs., Intel Corp., Hillsboro, OR, USA ; Tschanz, J. ; Erraguntla, V. ; Borkar, N.

This article deals with design challenges for high performance microprocessors. Device challenges including gate leakage, junction tunneling, junction depth scaling, parasitic series resistance, and short channel effects. Microprocessor frequencies are increasing every generation from additional architectural and circuit complexity, which demands higher level of integration and die size increase. To address these scaling challenges, devices, circuits and design methodologies need to evolve. Scaling gate oxide thickness is important for controlling short channel effects.

Published in:

VLSI Design, 2004. Proceedings. 17th International Conference on

Date of Conference:

2004

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