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This paper presents the concerns and techniques that are significant to both the circuit designers and developers of CAD tools for physical design and layout-based fault modeling and extraction. Current technology trends in VLSI with their impacts on the design flow in general and physical design in particular are introduced. The challenging issues in partitioning, floorplanning and placement, and routing are presented. Recent topics in deep sub-micron (DSM) regime are presented. Finally device scaling has led to blurring of the boundary between design and test and eroded the predictability of test quality based on classical stuck-at fault coverage. New fault models at the core of test generation to overcome the test quality crisis are described.