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Analysis of gate misalignment effect on the threshold voltage of double-gate (DG) ultrathin fully-depleted (FD) silicon-on-insulator (SOI) NMOS devices using a compact model considering fringing electric field effect

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3 Author(s)
Kuo, J.B. ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Sun, E.C. ; Lin, M.T.

This paper reports an analysis of gate misalignment effect on the threshold voltage of double-gate ultrathin fully depleted (FD) silicon on insulator (SOI) NMOS devices using a compact model considering fringing electric field effect. Using the conformal mapping transformation approach, a closed-form compact model considering the fringing electric filed effect above the non-gate overlap region has been derived to provide an accurate prediction of the threshold voltage behavior as verified by the 2D simulation results.

Published in:

Electron Devices for Microwave and Optoelectronic Applications, 2003. EDMO 2003. The 11th IEEE International Symposium on

Date of Conference:

17-18 Nov. 2003