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A cost-effective approach to the design and layout of a 14-b current-steering DAC macrocell

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3 Author(s)
Starzyk, J.A. ; Sch. of Electr. Eng. & Comput. Sci., Ohio Univ., Columbus, OH, USA ; Mohn, R.P. ; Liang Jing

This brief discusses the economical design of a 14-b current-steering digital-to-analog converter (DAC) macrocell for integration with other analog and digital macrocells in a system-on-chip (SOC). The DAC design is targeted for a standard 0.13-μm six-metal single-poly CMOS process. A novel algorithm sets the switching order of individual current sources and minimizes systematic mismatch errors. The design approach minimizes total fabrication cost of the SOC without a loss to specified DAC design requirements. Total macrocell design area is 2.9 mm2.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:51 ,  Issue: 1 )