Referenced Items are not available for this document.
In digital-to-analog converters (DACs), the sinc frequency response of the zeroth-order sample-and-hold causes a linear-phase notch response at f=1/Th, where Th is the hold time. In this brief, this notch is used to attenuate the lowest image signal below the sampling frequency by increasing the hold time longer than one sample period. This is implemented by using two time-interleaved DACs and a gated summing circuit with programmable on-times. The level of the spurious signals caused by mismatches between the parallel branches are analyzed, and the operation of the principle is verified experimentally.
Published in:
Circuits and Systems I: Regular Papers, IEEE Transactions on
(Volume:51
,
Issue:
1
)
Date of Publication: Jan. 2004
- Page(s):
- 178 - 181
- ISSN :
- 1549-8328
- INSPEC Accession Number:
- 8006160
- Digital Object Identifier :
- 10.1109/TCSI.2003.821285
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 07 April 2004
- Issue Date :
- Jan. 2004
- Sponsored by :
- IEEE Circuits and Systems Society
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