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In digital-to-analog converters (DACs), the sinc frequency response of the zeroth-order sample-and-hold causes a linear-phase notch response at f=1/Th, where Th is the hold time. In this brief, this notch is used to attenuate the lowest image signal below the sampling frequency by increasing the hold time longer than one sample period. This is implemented by using two time-interleaved DACs and a gated summing circuit with programmable on-times. The level of the spurious signals caused by mismatches between the parallel branches are analyzed, and the operation of the principle is verified experimentally.
Circuits and Systems I: Regular Papers, IEEE Transactions on (Volume:51 , Issue: 1 )
Date of Publication: Jan. 2004