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A realization of a below-1-V operational and 30-MS/s sample-and-hold IC with a 56-dB signal-to-noise ratio by applying the current-based circuit approach

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1 Author(s)
Sugimoto, Y. ; Electr., Electron., & Commun. Eng. Dept., Chuo Univ., Tokyo, Japan

This paper demonstrates the low-voltage and low-power operation of a MOS sample-and-hold circuit while preserving speed and accuracy, aiming at the realization of a pipelined low-voltage and low-power analog-to-digital converter on a system large-scale integrated circuit. It was fabricated by utilizing 0.35-μm CMOS technology. The main feature of this circuit is that all the input, signals, and output are in the current form. The circuit consists of simple current mirrors. In order to eliminate the signal-dependent current transfer ratio error, voltages at the drain terminals of mirror transistors are fixed as constant. A source degeneration resistor, which is a transistor in the triode operational region, is connected to a mirror transistor in order to alleviate the influence of the threshold and transconductance parameter variations. Control signals are boosted in voltage and applied to the gate of switch NMOS transistors in the signal path in order to reduce the on-resistance of analog switches. A differential configuration is adopted throughout the entire circuit and effectively cancels switch feedthrough errors. As a result, a 30-MS/s operation with a signal-to-noise ratio (SNR) of 56 dB from a 1-V supply has been achieved, when the input current is ±200 μA. The chip even operated down to 0.85 V with a 20-MHz clock. The SNR was measured as 50 dB with an input current of ±100 μA.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:51 ,  Issue: 1 )