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A new architecture for a vertical MOS transistor is proposed that incorporates a so-called dielectric pocket (DP) for suppression of short-channel effects and bulk punch-through. We outline the advantages that the DP brings and propose a basic fabrication process to realize the device. The design issues of a 50-nm channel device are addressed by numerical simulation. The gate delay of an associated CMOS inverter is assessed in the context of the International Technology Roadmap for Semiconductors and the vertical transistor is seen to offer considerable advantages down to the 100-nm node and beyond due to the dual channels and the ability to produce a 50-nm channel length with more relaxed lithography.