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A surface potential-based compact model of n-MOSFET gate-tunneling current

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7 Author(s)
Xin Gu ; Dept. of Electr. Eng., Pennsylvania State Univ., University Park, PA, USA ; Ten-Lon Chen ; Gildenblat, G. ; Workman, G.O.
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Aggressive scaling of the gate-oxide thickness has made gate-tunneling current an essential aspect of MOSFET modeling. This work presents a novel physics-based compact model of gate current in the n-MOSFET. A simplified version of the Esaki-Tsu formula is developed to calculate the tunneling current density, in which the original integral is approximated to retain the essential physics without sacrificing computational efficiency required in a compact model. The proposed model is surface potential-based in both the channel and source/drain overlap regions. The channel component of the gate current is physically partitioned into the source and drain parts using a symmetrically linearized version of the charge-sheet model. The partition is implemented in analytical form and accounts for the drain bias dependence of the channel component. A small number of adjustable parameters is sufficient to reproduce the experimentally observed bias and geometry dependence of the gate current for several advanced processes.

Published in:

Electron Devices, IEEE Transactions on  (Volume:51 ,  Issue: 1 )

Date of Publication:

Jan. 2004

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