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Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply pads in a CMOS digital circuit. In previous work, we develop a test procedure that can be used both to detect signal variations caused by defects and to obtain delay information in defect free chips. Phase spectra of transient signals obtained using discrete Fourier transform are shown to track path delays of defect-free chips under a wide range of process variations. However, in recent work, we were able to demonstrate through simulation experiments incorporating deep submicron transistor models, a circuit design and path sensitization scenario in which our existing TSA method is not able to yield accurate predictions of path delays. More specifically, a circuit composed of two inverter chains constructed with widely varying transistor sizes was shown to produce path delays that were weakly correlated across a set of worst case process models. In this paper, an alternative wavelet-based analysis of iDDT waveforms is shown to improve the accuracy of predicting multiple path delays under these conditions.