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Architectural synthesis Integrated with global placement for multi-cycle communication

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5 Author(s)
Jason Cong ; Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA ; Yiping Fan ; Han, G. ; Xun Yang
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Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous design, this requires the consideration of multi-cycle on-chip communication at the high level. In this paper, we present a new architectural synthesis system integrated with global placement, named MCAS (Multi-Cycle Architectural Synthesis), on top of the recently-proposed Regular Distributed Register (RDR) micro-architecture. The RDR architecture provides a regular synthesis platform for supporting multi-cycle communication. Novel architectural synthesis algorithms that integrate high-level synthesis with global placement have been developed in MCAS, including scheduling-driven placement and distributed controller generation, etc. Experimental results show that our methodology can achieve a clock period improvement of 31% and a total latency improvement of 24% on average compared to the conventional architectural synthesis flow.

Published in:

Computer Aided Design, 2003. ICCAD-2003. International Conference on

Date of Conference:

9-13 Nov. 2003