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A 9-16Gb/s clock and data recovery circuit with three-state phase detector and dual-path loop architecture

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2 Author(s)
Rezayee, A. ; Toronto Univ., Ont., Canada ; Martin, Ken

This paper describes the design and fabrication of a clock and data recovery circuit. This clock and data recovery circuit utilizes a novel half-rate three-state phase detector. The proposed phase detector is fully symmetric and has low propagation delay that makes it attractive for high speed applications. The proposed clock and data recovery circuit also implements a novel half-rate frequency detector. This frequency detector automatically remains disabled during the locked state. The proposed CDR circuit implements dual-path loop architecture. The dual path architecture suppresses the jitter peaking. The proposed clock recovery system is fabricated in a CMOS 0.18/spl mu/m technology. Measurements show that the CDR is functional for a data rate in the range of 9-16GHz. The circuit, including the output buffers, dissipates 310mW power from a 1.8V power supply for a 16Gb/s input data rate and 250mW power for a 10Gb/s input data rate. The peak-to-peak jitter of the recovered clock oscillating at 5 GHz and 8GHz are 10ps and 14ps, respectively. The effective die size is 1mm /spl times/ 0.8mm.

Published in:

Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European

Date of Conference:

16-18 Sept. 2003

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