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A 100 MHz to 3.5 GHz four-stage CMOS ring oscillator with quadrature outputs and oscillator core current consumption roughly proportional to operating frequency is presented. A novel oscillator topology consisting of a chain of four static single-ended CMOS inverters, four additional feedforward inverters and frequency control by steering the total oscillator core current is proposed. The circuit is implemented in a 0.18/spl mu/ standard CMOS technology. Oscillator core current consumption is 90/spl mu/A at 100 MHz and 9mA at 3.5 GHz with a 1.8V supply. Measured phase noise at 4 MHz offset is -114dBc/Hz at 100MHz and -106dBc/Hz at 3.5GHz oscillation frequency. Quadrature error is better than 3.5/spl deg/ over the 100 MHz to 3GHz frequency range.