Multiple-bit parallel-CDMA technique for an on-chip interface featuring high data transmission rate, small latency and high noise tolerance

We proposed a multiple-bit parallel-CDMA (MB/P-CDMA) interface featuring multi-valued voltage swing which enables to send more than one bit data at each clock. The voltage swing at each bus can be reduced to tens of milli-volts because of its high local noise tolerance nature, realizing efficient data transmission through MB/P-CDMA interface. MB/P-CDMA interface had been implemented with 0.35 /spl mu/m CMOS technology.