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Multiple-bit parallel-CDMA technique for an on-chip interface featuring high data transmission rate, small latency and high noise tolerance

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3 Author(s)
Shinsaku Shimizu ; Dept. of Electron. & Inf. Syst., Osaka Univ., Japan ; Matsuoka, T. ; Taniguchi, K.

We proposed a multiple-bit parallel-CDMA (MB/P-CDMA) interface featuring multi-valued voltage swing which enables to send more than one bit data at each clock. The voltage swing at each bus can be reduced to tens of milli-volts because of its high local noise tolerance nature, realizing efficient data transmission through MB/P-CDMA interface. MB/P-CDMA interface had been implemented with 0.35 /spl mu/m CMOS technology.

Published in:

Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European

Date of Conference:

16-18 Sept. 2003

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