A new technique for phase to sine mapping in direct digital frequency synthesizers (DDFSs) is presented. With respect to previously proposed piecewise linear Taylor and Chebyshev approaches, novel technique reduces either ROM size or arithmetic hardware complexity, without decreasing accuracy. Simulation results for a 0.35/spl mu/m technology show a substantial increase in performances with respect to Taylor and Chebyshev DDFSs.
Published in:
Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European
Date of Conference: 16-18 Sept. 2003