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Optimization of device dimensions for high-performance low-power architecture blocks

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4 Author(s)
Gemmeke, T. ; Electr. Eng. & Comput. Syst., RWTH Aachen Univ., Germany ; Gansen, M. ; Noll, T.G. ; Stockmanns, H.

A strategy for the implementation of energy-efficient architecture blocks is proposed. In enables mapping of algorithms to architectures at maximal efficiency based on automized optimization of device dimensions of elementary basic cells. As an example, the design of a high-throughput low-power FIR-filter is described. The effectiveness of the proposed strategy is confirmed by comparison with state-of-the-art filter macros.

Published in:

Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European

Date of Conference:

16-18 Sept. 2003