By Topic

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

9 Author(s)

Ground bounce is a major contributor to substrate noise generation due to the resonance caused by the inductance and the VDD-VSS admittance that consists of the on-chip digital circuit capacitance of the MOS transistors, the decoupling, and the parasitics arising from the interconnect. This paper addresses (1) the dependence of the VDD-VSS admittance on the different states of the circuit and the interconnect, and (2) the computation of total supply current with ground bounce. The VDD-VSS admittances of several test circuits are computed with 13% maximum error relative to the measurements on a test ASIC fabricated in a 0.18/spl mu/m CMOS process on a high-ohmic substrate with 18/spl Omega/cm resistivity. It is also shown that this admittance depends on the connectivity of the gates to the supply rail rather than their connectivity among each other.

Published in:

Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European

Date of Conference:

16-18 Sept. 2003