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Ground bounce is a major contributor to substrate noise generation due to the resonance caused by the inductance and the VDD-VSS admittance that consists of the on-chip digital circuit capacitance of the MOS transistors, the decoupling, and the parasitics arising from the interconnect. This paper addresses (1) the dependence of the VDD-VSS admittance on the different states of the circuit and the interconnect, and (2) the computation of total supply current with ground bounce. The VDD-VSS admittances of several test circuits are computed with 13% maximum error relative to the measurements on a test ASIC fabricated in a 0.18/spl mu/m CMOS process on a high-ohmic substrate with 18/spl Omega/cm resistivity. It is also shown that this admittance depends on the connectivity of the gates to the supply rail rather than their connectivity among each other.