A high-speed logic circuit family with interdigitated array structure for deep sub-micron IC design

This paper presents a new high-speed logic circuit family based on an interdigitated array structure for deep sub-micron IC design. The circuit family consists of a comparator, a priority encoder, and an incrementor for 128-bit data processing. The proposed circuit includes three schemes: 1) a divided column scheme, 2) a programmable sense-amplifier activation scheme, and 3) an interdigitated column scheme. These schemes achieved a 22.2% delay reduction and a 37.5% chip area reduction over the conventional high-speed array logic circuit in a 0.13-/spl mu/m CMOS technology with a supply voltage of 1.2 V. A module generator of the logic circuit family was also developed to enhance the process portability for IP-based design.