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In evaluating a design, it is critical to extract the best energy-delay curve, often performed with optimization tools. Such curve can be quickly obtained from our proposed numerical method where the energy at each delay target is minimized by redistribution of gate sizes to balance delay and energy consumption among different stages of the design. Compared to delay-optimized solution, the resulting energy saving is significant, 30%-50%, depending on delay target and design. The results are confirmed with simulation, using Fujitsu's 0.11/spl mu/m, 1.2V CMOS technology.
Date of Conference: 16-18 Sept. 2003