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A 1-V 13-mW 2.5-GHz double-rate phase-locked loop with phase alignment for zero delay

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2 Author(s)
Leung, G.C.T. ; Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China ; Luong, H.C.

A 1-V 2.5-GHz double-rate phase-locked loop (PLL) with zero clock skew fabricated in a 0.18-/spl mu/m standard CMOS technology is presented. A novel phase-alignment technique is proposed to achieve an inherent zero delay between the input reference and the output. Operated with the input and output frequencies of 1.25 GHz and 2.50 GHz, respectively, and with a 1-V supply voltage, the PLL prototype measures a rms jitter of 1.3 ps and a peak-to-peak jitter of 8.1 ps while consuming 13 mW and occupying a chip area of 2.5 mm/sup 2/.

Published in:

Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European

Date of Conference:

16-18 Sept. 2003