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Silicon clean impact on 90nm CMOS devices performance

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6 Author(s)
Carrere, J.-P. ; ST Microelectron., Crolles, France ; Bernard, H. ; Petitdidier, S. ; Beverina, A.
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We show in this paper that 90 nm NMOS performance can be enhanced by minimizing the silicon consumption due to the wet cleaning processes of the double gate oxide module. A complete analysis is presented, showing a good correlation between the increase of the electron mobility and the reduction of the silicon clean consumption. We also discuss why the PMOS behavior is not altered by these cleans. Moreover, a 4% delay reduction on ring oscillators is measured. Finally, both the thick and thin gate oxide quality has been preserved: this shows that an ideal compromise has been found between the silicon cleaning efficiency and the device performance improvement.

Published in:

European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on

Date of Conference:

16-18 Sept. 2003