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50-gbit/s InP HEMT 4 : 1 multiplexer/1 : 4 demultiplexer chip set with a multiphase clock architecture

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6 Author(s)
Sano, K. ; NTT Photonics Labs., NTT Corp., Kanagawa, Japan ; Murata, K. ; Kitabayashi, H. ; Sugitani, S.
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A 50-Gbit/s InP high electron-mobility transistor (HEMT) chip set of 4 : 1 multiplexer (MUX) and 1 : 4 demultiplexer (DMUX) integrated circuits (ICs) with a multiphase clock (MPC) architecture is described. The MPC architecture employs a quarter-rate four-phase clock generated by a toggle flip-flop inside the ICs, which reduces the number of circuit elements and lowers the power consumption. The fabricated 4 : 1 MUX and 1 : 4 DMUX ICs exhibited 50-Gbit/s error-free operations for 231-1 pseudorandom bit sequences with 1.71- and 1.42-W power consumption, respectively. Compared to conventional tree-type 4 : 1 MUX and 1 : 4 DMUX ICs using InP HEMTs, the MPC 4 : 1 MUX and 1 : 4 DMUX ICs operate at the same operating speed with less than one-third power consumption.

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Microwave Theory and Techniques, IEEE Transactions on  (Volume:51 ,  Issue: 12 )