By Topic

A library compatible driver output model for on-chip RLC transmission lines

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
K. Agarwal ; Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA ; D. Sylvester ; D. Blaauw

This paper presents a new library-compatible approach to gate-level timing characterization in the presence of resistive/inductive/capacitive (RLC) interconnect loads. We show that for a gate driving an RLC interconnect, the driver-output waveform exhibits inflection points and, hence, the traditional approach of approximating driver output with a saturated ramp is highly inaccurate. We describe a two-ramp model based on transmission-line theory that accurately predicts both the 50% delay and waveform shape (slew rate) at the driver output when inductive effects are significant. The approach does not rely on piecewise linear Thevenin voltage sources and is compatible with existing library characterization methods. Results are compared with SPICE and demonstrate typical errors under 10% for both delay and slew rate. We also propose a new criterion for evaluating the importance of on-chip inductance by comparing rise time at the driver output with the time of flight.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:23 ,  Issue: 1 )