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A DDS-based PLL for 2.4-GHz frequency synthesis

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4 Author(s)
Bonfanti, A. ; Dept. of Electron. & Inf. Technol., Politecnico di Milano, Italy ; Amorosa, F. ; Samori, C. ; Lacaita, A.L.

In this transactions brief, we present a direct digital synthesizer (DDS)-based phase-locked loop (PLL), for frequency synthesis at 2.4 GHz with 80-MHz tuning range. The DDS signal is mixed with the voltage-control oscillator output in the PLL feedback path. This solution helps in avoiding some of the typical tradeoffs in PLL. In particular, it is possible to achieve a very high-frequency resolution together with fast settling and spectral purity. These characteristics are often incompatible both in integer and fractional dividers PLL. A prototype was fabricated on PCBs and tested. The settling time is about 3 μs for 0.1 ppm (240 Hz) accuracy. Worst-case spurs are -53 dBc at 8-MHz offset from the carrier. The integrated phase noise in the band 1 kHz -1 MHz is 0.9° rms. This architecture is also suitable for direct frequency modulation, without necessitating any calibration system.

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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:50 ,  Issue: 12 )