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Novel MOS translinear loop topologies for very low-voltage applications are presented. The inclusion of dc level shifting, together with a novel biasing scheme based on two MOS transistors in the triode region, allows the operation of the loops at supply voltages as low as VGS+2VDSsat maintaining at the same time a large dynamic range. Several current-mode translinear circuits, both static and dynamic, i.e., geometric mean, squarer/divider, multiplier and square-root-domain filters, are implemented following this approach, demonstrating on silicon the proposed techniques.
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on (Volume:50 , Issue: 12 )
Date of Publication: Dec. 2003