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A capacitorless double gate DRAM technology for sub-100-nm embedded and stand-alone memory applications

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3 Author(s)
Kuo, C. ; Intel Corp., Santa Clara, CA, USA ; Tsu-Jae King ; Chenming Hu

A capacitorless, asymmetric double gate DRAM (DG-DRAM) technology is presented. Its double gate, thin body structure reduces dopant fluctuation effects, off-state leakage, and disturb problems. The cell's large body coefficient amplifies small gains of body potential into increased drain current. Experimental measurements of DG-DRAM were made using recessed channel SOI n-MOSFETs. No significant degradation in programming, retention, and read behavior was observed after 1011 cycles. Cell geometry, operating voltages, and material quality should be considered for DG-DRAM in embedded and stand-alone applications. The feasibility of DG-DRAM in future high density CMOS memories depends on issues such as manufacturability, soft error reliability, and tail bit distribution.

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Electron Devices, IEEE Transactions on  (Volume:50 ,  Issue: 12 )