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An asynchronous ternary logic signaling system

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2 Author(s)
T. Felicijan ; Dept. of Comput. Sci., Univ. of Manchester, UK ; S. B. Furber

This paper presents a new approach to an on-chip asynchronous transmission system suitable for next generation asynchronous on-chip networks. It implements multivalued logic to reduce the number of wires and a low-voltage swing for lower dynamic power dissipation. Furthermore, the transmission system described here enjoys fully static design and has zero static power consumption. Two versions of the transmitter circuit and the receiver are described. The proposed signaling scheme is compared to a classical dual-rail signaling system with regard to speed, power consumption, and reliability. The simulation results show that the asynchronous ternary logic signaling (ATLS) system delivers over 70% higher bandwidth per wire and consumes over 50% less power than the dual-rail signaling system on 10-mm-long on-chip interconnection.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:11 ,  Issue: 6 )