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This paper presents new solutions for reducing the power consumption BIST environment (Pseudorandom Test Pattern Generator-PTPG and Signature Analyzer-SA). The key idea behind this technique is based on the designing a new structure of LFSR (Linear Feedback Shift Register) to generate more than one pseudo random bit per one clock pulse and a new SA structure for compressing several test responses bits per one clock pulse. The proposed method can be used within ≪test-per-clock≫ BIST architecture, as well as may be extended for the ≪test-per-scan≫ BIST technique.
Date of Conference: 18-22 Feb. 2003