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HW/SW partitioned optimization and VLSI-FPGA implementation of the MPEG-2 video decoder

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3 Author(s)
Verderber, M. ; Fac. of Electr. Eng., Univ. of Ljubljana, Slovenia ; Zemva, A. ; Lampret, D.

In this paper, we propose an optimized real-time MPPEG-2 video decoder. The decoder has been implemented in one FPGA device as a HW/SW partitioned system. We carried out time/power-consumption analysis and optimization of the MPEG-2 decoder. On the basis of the achieved results, we decided for HW implementation of the IDCT and VTD algorithms. Remaining parts were realized in SIV with 32-bit RISC processor. MPEG-2 decoder (RISC processor, IDCT core, VLD core) has been described in Verilog/VHDL and implemented in Virtex 1600E FPGA. Finally, the decoder has been tested on the Flextronics prototyping board.

Published in:

Design, Automation and Test in Europe Conference and Exhibition, 2003

Date of Conference:

2003